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 Middle Power Class-D Speaker Amplifiers
Class-D Speaker Amplifier for Digital Input with Built-in DSP
BM5446EFV
No.10075EBT13
Description BM5446EFV is a Class D Speaker Amplifier with built-in DSP (Digital Sound Processor) designed for Flat-panel TVs in particular for space-saving and low-power consumption, delivers an output power of 20W+20W. This IC employs state-of-the-art Bipolar, CMOS, and DMOS (BCD) process technology that eliminates turn-on resistance in the output power stage and internal loss due to line resistances up to an ultimate level. With this technology, the IC can achieve high efficiency of 86% (10W+10W output with 8 load). In addition, the IC is packaged in a compact reverse heat radiation type power package to achieve low power consumption and low heat generation and eliminates necessity of external heat-sink up to a total output power of 40W. This product satisfies both needs for drastic downsizing, low-profile structures and many function, high quality playback of sound system. Features 1) This IC includes the DSP (digital sound processor) for Audio signal processing for Flat TVs. 2) This IC has two input systems of digital audio interface. 2 (I S/LJ/RJ format, LRCLK: 32 kHz/ 44.1kHz / 48kHz, SYS_CLK: 256fs / 512fs, BCLK: 48fs / 64fs, SDATA: 16 / 20 / 24bit) 3) With wide range of power supply voltage, it is possible to operate with single power supply. (Vcc = 10~26V) 4) With high efficiency and low heat dissipation contributing to miniaturization, slim design, and also power saving of the system. 5) S/N of the system can be optimized by adjusting the gain selection in 16 steps. (20~35dB,1dB/step) 6) With built-in feedback circuitry at the output, prevents the decrease in sound quality due to change in power supply voltage. In addition, low noise and low distortion are achieved. 7) With a built-in DAC provides best stereo-output for headphone function. As a result, the selection of output of the digital input in two systems is possible. 8) It has additional S/PDIF output for the LINE output usage. 9) Eliminates pop-noise generated during the power supply on/off. High quality muting performance is realized by using the soft-muting technology. 10) This IC is built-in with various protection functions for highly reliability design. (High temperature protection, Under voltage protection, Output short protection, Output DC-Voltage protection and Clock stop protection). Applications Flat Panel TVs (LCD, Plasma), Home Audio, Desktop PC, Amusement equipments, Electronic Music equipments, etc.
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1/32
2010.05 - Rev.B
BM5446EFV
Absolute maximum ratings (Ta=25) Parameter Supply voltage Symbol VCC Ratings 30 2.0 Power dissipation Pd 4.5 6.2 Input voltage Open-drain terminal voltage Operating temperature range Storage temperature range Maximum junction temperature VIN VERR Topr Tstg Tjmax -0.3 ~ 4.5 -0.3 ~ 30 -25 ~ +85 -55 ~ +150 +150 Unit V W W W V V
Technical Note
Conditions Pin 27, 30, 31, 51, 52 *3 *4 *5 Pin 5 ~ 14, 22 Pin 26 *1 *1 *1*2
*1 The voltage that can be applied reference to GND (Pin 4, 36, 37, 45, 46) and VSS (Pin 15, 20). *2 Do not, however exceed Pd and Tjmax=150. *3 70mmx70mmx1.6mm, FR4, 1-layer glass epoxy board (Copper on bottom layer 0%) Derating in done at 16mW/ for operating above Ta=25. *4 70mmx70mmx1.6mm, FR4, 2-layer glass epoxy board (Copper on bottom layer 100%) Derating in done at 36mW/ for operating above Ta=25. There are thermal via on the board. *5 70mmx70mmx1.6mm, FR4, 4-layer glass epoxy board (Copper on bottom layer 100%) Derating in done at 49.6mW/ for operating above Ta=25. There are thermal via on the board.
Operating conditions (Ta=25) Parameter Supply voltage Minimum load impedance (Speaker Output) Minimum load impedance (DAC Output)
*6 Do not, however exceed Pd. * No radiation-proof design.
Symbol VCC RL_SP RL_DA
Ratings 10 ~ 26 5.4 20
Unit V k
Conditions Pin 27, 30, 31, 51, 52 *6 Pin 24, 25 *1 *2
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2/32
2010.05 - Rev.B
BM5446EFV
Technical Note
Electrical characteristics (Unless otherwise specified Ta=25,Vcc=13V,f=1kHz,RL_SP=8,RL_DA=20k,RESETX=3.3V,MUTEX=3.3V,PDX=3.3V, Gain=20dB, DSP: Through, fs =48kHz) Limits Parameter Symbol Unit Conditions Min. Typ. Max. Total circuit Circuit current Circuit current (Power down mode) Open-drain terminal Low level voltage Regulator output voltage 1 Regulator output voltage 2 Regulator output voltage 3 High level input voltage Low level input voltage Input current (Input pull-up terminal) Input current (Input pull-down terminal) Input current (SCL, SDA terminal) Output current (SCL, SDA terminal) High level output voltage (S/PDIF output terminal) Low level output voltage (S/PDIF output terminal) Speaker Output Maximum momentary output power 1 Maximum momentary output power 2 Total harmonic distortion Crosstalk Output noise voltage (Sampling mode) Residual noise voltage (Mute mode) PO1 PO2 THDSP CTSP VNO_SP VNOR_SP fPWM1 PWM sampling frequency fPWM2 fPWM3 DAC Output Maximum output voltage Channel Balance Total harmonic distortion Crosstalk Output noise voltage Residual noise voltage VOMAX CB THDDA CTDA VNO_DA VNOR_DA 0.85 -1 65 1.0 0 0.05 80 10 3 1 0.5 20 10 Vrms dB % dB Vrms Vrms 0dBFS,THD+n=1% 0dBFS -20dBFS,BW=2020kHz 0dBFS,BW=IHF-A -dBFS,BW=IHF-A MUTEX=0V,PDX=0V, -dBFS,BW=IHF-A 65 10 20 0.07 80 140 5 512 705.6 768 280 10 W W % dB Vrms Vrms kHz kHz kHz THD+n=10%,Gain=26dB Vcc=18V,THD+n=10%,Gain=26d B PO=1W,BW=2020kHz PO=1W,BW=IHF-A -dBFS,BW=IHF-A MUTEX=0V,-dBFS,BW=IHF-A fs=32kHz fs=44.1kHz fs=48kHz *7 *7 *7 *7 *7 *7 *7 *7 *7 ICC1 ICC2 VERR VREG_G VREG_3 VREG_15 VIH VIL IIL IIH II IO VOH VOL 5.0 3.0 1.3 2.5 0 50 30 -1 2.75 60 2.5 5.5 3.3 1.5 100 70 0 0 3.3 0 120 5 0.8 6.0 3.6 1.7 3.3 0.8 150 105 1 0.55 mA mA V V V V V V A A A A V V Pin 27, 30, 31, 51, 52,No load Pin 27, 30, 31, 51, 52,No load RESETX=0V, MUTEX=0V,PDX=0V Pin 26,IO=0.5mA Pin 28, 54 Pin 3 Pin 16 Pin 5 ~ 14, 22 Pin 5 ~ 14, 22 Pin 5 ~ 9,VIN = 0V Pin 10 ~ 12, 22,VIN = 3.3V Pin 13, 14,VIN = 3.3V Pin 13, 14,VIN = 0V Pin 23,IO=-0.6mA Pin 23,IO= 0.6mA
*7 These items show the typical performance of device and depend on board layout, parts, and power supply. The standard value is in mounting device and parts on surface of ROHM's board directly.
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3/32
2010.05 - Rev.B
BM5446EFV
DSP Block Functional Overview 1) Main Signal line function No. Function 1 2 3 Pre-scalar DC cut HPF Channel Mixer Lch / Rch synchronous control +24 ~ -103dB (0.5dB step),-dB FC : 1Hz
Technical Note
Specification
4
P2Volume (Perfect Pure Volume)
Mixing of the sound of the left and right channel of the input digital signal to DSP is set up. There are some scenes when sound becomes large suddenly, like the explosion-scene in TV commercial or in an action movie. The "P2Volume" function controls volume automatically and adjusts the output level. It makes easy to hear small whisper voice, and is adjusted. Attack time : 1ms ~ 40ms (8steps) Recovery time : 0.25s ~ 10s (16 steps) Peaking filter is used. Lch / Rch Concurrent control Soft transition function Fc Select : Same as 7 Band Parametric Equalizer Gain Select : 18dB (0.5dB step) Q (Quality Factor) : Same as 7 Band Parametric Equalizer Low shelf filter is used. Lch / Rch Concurrent control Soft transition function Fc Select : Same as 7 Band Parametric Equalizer Gain Select : 18dB (0.5dB step) Q (Quality Factor) : Same as 7 Band Parametric Equalizer
5
BASS
6
MIDDLE
Peaking filter is used. Lch / Rch Concurrent control Soft transition function Fc Select : Same as 7 Band Parametric Equalizer Gain Select : 18dB (0.5dB step) Q (Quality Factor) : Same as 7 Band Parametric Equalizer Peaking filter is used. Lch / Rch Concurrent control Soft transition function Fc Select : Same as 7 Band Parametric Equalizer Gain Select : 18dB (0.5dB step) Q (Quality Factor) : Same as 7 Band Parametric Equalizer High shelf filter is used. Lch / Rch Concurrent control Soft transition function Fc Select : Same as 7 Band Parametric Equalizer Gain Select : 18dB (0.5dB step) Q (Quality Factor) : Same as 7 Band Parametric Equalizer
7
TREBLE
8 9
Scalar 1 Pseudo Stereo
10
Matrix Surround 3D
11
P Bass (Perfect Pure Bass)
2
Lch / Rch Concurrent control +24 ~ -103dB (0.5dB step), -dB A stereo-feel sound is reproduced for a monophonic sound by signal processing. 3 steps : Pseudo Stereo OFF / Pseudo Stereo ON (Weak) / Pseudo Stereo ON (Strong) Matrix Surround 3D of a wider sweet spot, and it also with little prolonged viewing and listening with a feeling of fatigue. The acoustic field which does not spoil a vocal feeling of the normal position is played back. Surround : ON / OFF function Loop : ON / OFF function Surround gain select : 16 steps Clear deep Bass with low distortion. Lch / Rch Concurrent control Soft transition function Frequency select : 4 steps Gain select : 0 ~ 15dB (1dB step) Real, pure and crystal clear sound. Lch / Rch Concurrent control Soft transition function Gain select : 0 ~ 15dB (1dB step) Lch / Rch Concurrent control +24 ~ -103dB (0.5dB step), - dB
12
P Treble (Perfect Pure Treble) Scalar 2
2
13
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4/32
2010.05 - Rev.B
BM5446EFV
Technical Note
No.
Function
Specification Peaking filter is used. (Possible to set the 5 coefficients directly for b0,b1,b2,a1,a2) Lch / Rch Concurrent control Fc select : Setup of 61 divisions (20Hz ~ 20kHz) is possible. Gain select : 18dB ( 0.5dB step ) Q(Quality Factor) : 0.33, 0.43, 0.56, 0.75, 1.0, 1.2, 1.5, 1.8, 2.2, 2.7, 3.3, 3.9, 4.7, 5.6, 6.8, 8.2 +24 ~ -103dB ( 0.5dB step ), -dB Soft transition and soft mute function Lch / Rch Concurrent control, Sub-Woofer ch Independent control It decreases by 1dB step from a volume setting value. ( Lch/Rch : 0dB/-dB, 0dB/-126dB, 0dB/-125dB, , 0dB/0dB, , -125dB/0dB, -126dB/0dB, -dB/0dB ) Lch / Rch Concurrent control, Sub-Woofer ch Independent control +24 ~ -103dB (0.5dB step), -dB A clip with an arbitrary output amplitude is possible. Lch / Rch Concurrent control, Sub-Woofer ch Independent control
14
7-Band Parametric Equalizer
15
Volume
16 17 18
Balance Post-scaler Output Clipper
2) Sub Signal line function No. Function 19 Channel Mixer
20 21 22
LPF 3-Band Parametric Equalizer Volume
Specification Mixing of the sound of the left and right channel of the input digital signal to DSP is set up. Lch (Lch is input, (Lch+Rch)/2 is input, Rch is input), Rch (Rch is input, (Lch+Rch)/2 is input, Lch is input) LPF for Sub-Woofer Fc= 60Hz, 80Hz, 100Hz, 120Hz, 160Hz, 200Hz, 240Hz, 280Hz Peaking or low shelf or high shelf filter is used. Lch / Rch Concurrent control +24 ~ -103dB ( 0.5dB step ), -dB Soft transition and soft mute function Lch / Rch Concurrent control, Sub-Woofer ch Independent control It decreases by 1dB step from a volume setting value. ( Lch/Rch : 0dB/-dB, 0dB/-126dB, 0dB/-125dB, , 0dB/0dB, , -125dB/0dB, -126dB/0dB, -dB/0dB ) Lch / Rch Concurrent control, Sub-Woofer ch Independent control. +24 ~ -103dB (0.5dB step), -dB A clip with an arbitrary output amplitude is possible. Lch / Rch Concurrent control, Sub-Woofer ch Independent control.
23 24 25
Balance Post-scaler Output Clipper
SEL1 SDATA1
Pre Scalar
DC Cut HPF
Channel Mixer
BASS MIDDLE TREBLE
Scalar 1
Surround
Scalar 2
7 Band Parametric Equalizer
EVR Balance
Post Scalar & Clipper Post Scalar & Clipper
SEL2 SDATAO1 SPEAKER OUTPUT
SDATA2
Channel Mixer
LPF
3 Band Parametric Equalizer
EVR Balance
SDATAO2
Digital Audio Processing Signal Flow
SEL3
DAC
DSP Block diagram
S/PDIF OUTPUT ANALOG OUTPUT
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5/32
2010.05 - Rev.B
BM5446EFV
Technical Note
Electrical characteristic curves(VCC=13V,RL_SP=8,RL_DA=20k,Gain=20dB,fin=1kHz,fs=48kHz,by passing DSP) Measured by ROHM designed 4 layer board.
100 90 80 70 60 50 40 30 20 10 0 8 10 12 14 16 18 20 22 24 26 28 VCC(V) 44 40 36 32 28 24 20 16 12 8 4 0 3
OUTPUT POWER(W/ch)
Sampling
THD=10%
2 ICC(A)
VCC=13V
ICC(mA)
Mute
VCC=18V
1
THD=1%
0 8 10 12 14 16 18 20 22 24 26 28 VCC(V) 0 5 10 15 20 25 30 35 40 TOTAL OUTPUT POWER(W)
Fig.1 Current consumption - Power supply voltage
100 90 VOLTAGE GAIN(dB) EFFICIENCY(%) 80 70 60 50 40 30 20 10 0 0 2 4 6 8 10 12 OUTPUT POWER(W/ch) 30 28 26 24 22 20 18 16 14 12 10 10 100
Fig.2 Output power - Power supply voltage
0
Fig.3 Current consumption - Output power
NOISE FFT(dBV)
Po=1W L=22H C=0.47F Cg=0.068F
-20 -40 -60 -80 -100 -120 -140 1k 10k 100k 10
Without Signal BW=2020KHz
100
1k
10k
100k
FREQUENCY(Hz)
FREQUENCY(Hz)
Fig.4 Efficiency - Output power
Fig.5 Voltage gain - Frequency
Fig.6 FFT of Output noise voltage
100
100
BW=2020KHz
10 THD+N(%) THD+N(%) 10 1
Po=1W BW=2020KHz
CROSSTALK(dB)
1
6KHz 1KHz 100Hz
0.1 1 10 100
0.1
0.1 0.01 10 100 1k 10k 100k
0.01 0.001 0.01
0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100
BW=2020KHz
0.001
0.01
0.1
1
10
OUTPUT POWER(W)
FREQUENCY(Hz)
OUTPUT POWER(W)
Fig.7 THD+N - Output power
Fig.8 THD+N - Frequency
Fig.9 Crosstalk - Output power
0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 10
CROSSTALK(dB)
Po=1W BW=2020KHz
fin=300Hz Po=3.3W 5V/div
Speaker output
Speaker output
fin=300Hz Po=3.3W 5V/div
2V/div
MUTEX 10ms/div
MUTEX
2V/div 10ms/div
100
1k
10k
100k
FREQUENCY(Hz)
Fig.10 Crosstalk - Frequency
Fig.11 Wave form when Releasing Soft-start
Fig.12 Wave form when Activating Soft-mute
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6/32
2010.05 - Rev.B
BM5446EFV
Technical Note
Electrical characteristic curves(VCC=18V,RL_SP=8,RL_DA=20k,Gain=20dB,fin=1kHz,fs=48kHz,by passing DSP) Measured by ROHM designed 4 layer board.
100 90 VOLTAGE GAIN(dB) EFFICIENCY(%) 80 70 60 50 40 30 20 10 0 0 2 4 6 8 10 12 14 OUTPUT POWER(W/ch) 40 38 36 34 32 30 28 26 24 22 20 18 16 14 12 10 10
0 -20 NOISE FFT(dBV) -40 -60 -80 -100 -120 -140
Without Signal BW=2020KHz
Po=1W L=22H C=0.47F Cg=0.068F
100 1k 10k 100k
10
100
1k
10k
100k
FREQUENCY(Hz)
FREQUENCY(Hz)
Fig.13 Efficiency - Output power
Fig.14 Voltage gain - Frequency
Fig.15 FFT of output noise voltage
100
100
BW=2020KHz
10 THD+N(%) THD+N(%) 10
Po=1W BW=2020KHz
CROSSTALK(dB)
1
6KHz 1KHz 100Hz
1
0.1
0.1
0.01 0.001 0.01 0.1 1 10 100 OUTPUT POWER(W)
0.01 10 100 1k 10k 100k FREQUENCY(Hz)
0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100
BW=2020KHz
0.001 0.01
0.1
1
10
100
OUTPUT POWER(W)
Fig.16 THD+N - Output power
Fig.17 THD+N - Frequency
Fig.18 Crosstalk - Output power
0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 10
CROSSTALK(dB)
Po=1W BW=2020KHz
100
1k
10k
100k
FREQUENCY(Hz)
Fig.19 Crosstalk - Frequency
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7/32
2010.05 - Rev.B
BM5446EFV
Pin configuration and Block diagram
Technical Note
1 2 3 4 5 6
FILP FILA REG_3 GNDA
VCCP1
REG_G1
54 NC 53 52 51 NC 50 49
I2S/LJ/ 7 8 9 10 11 12
Control Interface
RJ Interface
Driver 1P REG_G1
48 47 46
Driver 1N
GNDP1
45 44 43 REG_G1 42 NC 41 40 REG_G2 39 38
13 14 15 16 17 18 19 20 21 22 23 24
I2C Interface
DSP
PWM Modulator
VSS1 REG_15 TEST1 VDD PLL
GNDP2
Driver 2N
37 36 35 REG_G2
VSS2 TEST2 Driver 2P
34 33 NC 32 31
DAC 25 26 27 VCCA
High Temperature Protection Under Voltage Protection Clock Stop Protection Output Short Protection Output DC Voltage Protection
VCCP2
30 NC 29 REG_G2 28
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8/32
2010.05 - Rev.B
BM5446EFV
Pin function explanation (Provided pin voltages are typ. Values) Pin No. Pin name Pin voltage Pin explanation
Technical Note
Internal equivalence circuit
52,51 30,31
54 28
REG_G1 REG_G2
5.5V
Internal power supply pin for ch1 Gate driver Internal power supply pin for ch2 Gate driver Please connect the capacitor.
54 28 550K 45,46 36,37
27
Bias pin for PWM signal 1 FILP 1.752.55V Please connect the capacitor.
1
4
27
Bias pin for Analog signal 2 FILA 2.5V Please connect the capacitor.
4
27
50K 2 50K
Internal power supply pin for Digital circuit 3 REG3 3.3V Please connect the capacitor.
4 3 500K
4
GNDA
0V
GND pin for Analog signal
18
5
SYS_CLK
3.3V
System-Clock input pin
5
15,20
18
6 7 8 9
BCLK LRCLK SDATA1 SDATA2
3.3V
Digital audio signal input pin
6,7 8,9
15,20
10
RESETX
11
MUTEX
0V
12
PDX
Reset pin for Digital circuit H: Reset OFF L: Reset ON Speaker output mute control pin H: Mute OFF L: Mute ON Power down control pin H: Power down OFF L: Power down ON
18
10,11,12
15,20
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9/32
2010.05 - Rev.B
BM5446EFV
Pin No.
Technical Note
Pin name
Pin voltage
Pin explanation
Internal equivalence circuit
13
13
SCL
I2C transmit clock input pin
15,20
14
14
SDA
I2C data input/output pin
15,20
15 20
VSS1 VSS2
0V
GND pin for Digital I/O
18
16
REG_15
1.5V
Internal power supply pin for Digital circuit
16
15,20
18
Test pin 17 TEST1 Please connect to VSS.
15,20 17
18
VDD
3.3V
Power supply pin for Digital I/O
18
19
PLL
1V
PLL's filter pin
19
15,20
18
Test pin 21 TEST2 0V Please connect to VSS.
15,20
18
21
22
ADDR
0V
I2C Slave address select pin
22
15,20
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10/32
2010.05 - Rev.B
BM5446EFV
Pin No.
Technical Note
Pin name
Pin voltage
Pin explanation
Internal equivalence circuit
18
23
OUT_SPDIF
S/PDIF output pin
23
15,20
27
24 25
OUT_DAC2 OUT_DAC1
ch2 DAC output pin ch1 DAC output pin 2.5V Please connect it with the latter part circuit through the capacitor.
4 24,25 50K
Error flag pin Please connect pull-up resistor. H: While Normal L: While Error
27 500 26
26
ERROR
3.3V
4
27 30 31 33 34 35 36 37 38 39 40 42 43 44 45 46 47 48 49 51 52 29 32 41 50 53
VCCA VCCP2 OUT2P BSP2P GNDP2 OUT2N BSP2N BSP1N OUT1N GNDP1 BSP1P OUT1P VCCP1
Vcc Vcc Vcc0V 0V Vcc0V Vcc0V 0V Vcc0V
Power supply pin for Analog signal Power supply pin for ch2 PWM signal
30,31
Output pin of ch2 positive PWM signal Please connect to Output LPF. Boot-strap pin of ch2 positive Please connect the capacitor. GND pin for ch2 PWM signal Output pin of ch2 negative PWM signal Please connect to Output LPF. Boot-strap pin of ch2 negative Please connect the capacitor. Boot-strap pin of ch1 negative Please connect the capacitor. Output pin of ch1 negative PWM signal Please connect to Output LPF. GND pin for ch1 PWM signal Boot-strap pin of ch1 positive Please connect the capacitor. Output pin of ch1 positive PWM signal Please connect to Output LPF. Power supply pin for ch1 PWM signal
35 40 33,34 38,39
36,37
51,52 42 47 43,44 48,49
45,46
N.C.
Non connection pin
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11/32
2010.05 - Rev.B
BM5446EFV
RESETX pin function RESETX State of Digital block (10pin) L H Reset ON Reset OFF
Technical Note
PDX pin,MUTEX pin function PDX MUTEX (12pin) (11pin) L H H L or H L H
Power Down ON OFF
DAC output (24,25pin) HiZ_Low Normal operation
PWM output (33,34,38,39,43,44,48pin) HiZ_Low Normal operation
Input digital audio sampling frequency (fs) explanation PWM sampling frequency, Soft-start, Soft-mute time, and the detection time of the DC voltage protection in the speaker depends on sampling frequency (fs) of the digital audio input. Sampling frequency of the Digital audio input (fs) 32kHz 44.1kHz 48kHz PWM sampling frequency (fpwm) 512kHz 705.6kHz 768kHz DC voltage protection in the speaker detection time 64msec. 46msec. 43msec.
Soft-start / Soft-mute time 64msec. 46msec. 43msec.
For voltage gain (Gain setting) BM5446EFV prescribe voltage gain at speaker output (BTL output) under the definition 0dBV (1Vrms) as full scale input of the digital audio input signal. For example, digital audio input signal = Full scale input, Gain setting = 20dB, Load resistance 2 RL_SP= 8 will give speaker output (BTL output) amplitude as 10Vrms. (Output power Po = Vo /RL_SP=12.5W )
Speaker output DSP output signal SDATAO1 will be output to the speaker. (SDATAO2 will not be output to the speaker. DAC output can be selected either from DSP output signal SDATAO1 or SDATAO2.)
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12/32
2010.05 - Rev.B
BM5446EFV
I2C Bus control signal specification 1) Electrical characteristics and Timing of Bus line and I/O stage
Technical Note
SDA
tBUF
tF tLOW tR
tHD;STA
SCL
tHD;STA
tHD;DAT
tHIGH
tSU;DAT
tSU;STA
tSU;STO
P
S
Sr
P
SDA and SCL bus line characteristics(Unless otherwise specified Ta=25, VCC=13V) Parameter 1 2 3 4 5 6 7 8 9 10 11 12 SCL clock frequency Bus free time between "Stop" condition and "Start" condition Hold-time of (sending again)"Start" condition. After this period the first clock pulse is generated. SCL clock's LOW state Hold-time SCL clock's HIGH state Hold-time Set-up time of sending again "Start" condition Data hold time Data set-up time *2 Rise-time of SDA and SCL signal Fall-time of SDA and SCL signal Set-up time of "Stop" condition Capacitive load of each bus line Symbol fSCL tBUF tHD;STA tLOW tHIGH tSU;STA tHD;DAT tSU;DAT tR tF tSU;STO Cb High speed mode Min. Max. 0 400 1.3 0.6 1.3 0.6 0.6 0 *1 500/250/150 20+Cb 20+Cb 0.6 300 300 400 Unit kHz s s s s s s ns ns ns s pF
The above-mentioned numerical values are all the values corresponding to VIH min and the VIL max level. *1 To exceed an undefined area on the fall-edge of SCL (VIH min of the SCL signal), the transmitting set should internally offer the holding time of 300ns or more for the SDA signal. *2 The data set-up time is different according to the setting of SYS_CLK. When SYS_CLK=128fs it is 500ns, for SYS_CLK=256fs it is 250ns, for SYS_CLK=512fs it will be 150ns. *3 SCL and SDA pin is not corresponding to threshold tolerance of 5V. Please use it within 4.5V of the absolute maximum rating.
2) Command interface I2C Bus control is used for command interface between host CPU. It not only writes but also it is possible to read it excluding a part of register. In addition to "Slave Address " , set and write 1 byte of "Select Address " to read out the 2 data. I C bus Slave mode format is illustrated below. MSB LSB MSB LSB MSB S Slave Address A Select Address A LSB Data A P
S : Start Condition Slave Address : The data of eight bits in total is sent putting up bit of Read mode (H) or Write mode (L) after slave address (7bit) set with the terminal ADDR. (MSB first) A : The acknowledge bit adds to data that the acknowledge is sent and received in each byte. When data is correctly sent and received,"L"is sent and received. There was no acknowledgement for "H". Select Address : The select address in one byte is used.(MSB first) Data : Data byte is sent and received data(MSB first) P : Stop Condition
SDA SCL
Start Condition SDA SCL="H"
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MSB
6
5
LSB
Stop condition SDA SCL="H"
(c) 2010 ROHM Co., Ltd. All rights reserved.
13/32
2010.05 - Rev.B
BM5446EFV
3) Slave Address While ADDR pin (22pin) is"L" MSB A6 A5 A4 1 0 0 While ADDR pin (22pin) is"H" MSB A6 A5 A4 1 0 0 4) Writing of data Basic format S Slave Address A Select Address : Auto-increment format S Slave Address A Select Address : A Data 1 A Data 2 : A A Data A P : Slave to Master
Technical Note
A3 0
A2 0
A1 0
A0 0
LSB R/W 1/0
A3 0
A2 0
A1 0
A0 1
LSB R/W 1/0
Master to Slave,
Data 3...N
A
P
Master to Slave,
Slave to Master
5)Reading of data First of all, the address ( 20h in the example) for reading is written in the register of the D0h address at the time of reading. In the following stream, data is read after the slave address. Please do not return the acknowledge when you end the reception. S Slave Address (ex.) 80h S Slave Address (ex.) 81h : A Req_Addr D0h A **h Data 1 **h : A A Select Address 20h Data 2 A A P
A **h
Data N
P
Master to Slave
Slave to MasterA : With Acknowledge : Without Acknowledge
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14/32
2010.05 - Rev.B
BM5446EFV
6) Instruction Code Chart (Select Address)
LSB MSB 0 1 2 3 4 5 6 7 8 9 A PLLA Power B Stage C Read Base D Address E TEST F Mode LSB MSB 0 1 2 3 4 5 6 7 8 9 A PLLA Sync Detect3 Sync Detect4 Refresh Test8 PU Setting 8 Initial Setting MCLK DIV TEST Mode2 TEST Mode1 Setting 9 A
2
Technical Note
0
1 RAM Clear SPDIF OUT Setting1 DC Cut HPF Sub Clipper Setting1 BASS Frequency 7Band1 Frequency 7Band5 Frequency Pseudo Stereo 3Band1 Frequency
2
3 Input SEL S-P2,S-P1
4 Output SEL P-S2,P-S1
5 SPDIFO Output SEL
6
7
I/O Setting CLK Setting SPDIF MUTE Setting DSP PRE Scaler Volume Setting Sub Clipper Sub Clipper 2 P Volume ON/OFF DSP BASS TONE Control DSP 7Band1 7BandP-EQ Control DSP 7Band5 7BandP-EQ Control DSP Surround Sound Effect Setting DSP 3Band1 3BandP-EQ Control
SPDIF OUT Setting2 CH Mixer1 DSP Sub Clipper Setting2 BASS Quality factor 7Band1 Quality factor 7Band5 Quality factor 2 P Bass Setting1 3Band1 Quality factor
SPDIF OUT CH Mixer2 DF2, DF1 P V Setting1 BASS Gain 7Band1 Gain 7Band5 Gain 2 P Bass Setting2 3Band1 Gain
2
Scaler1 Setting P V_MIN MIDDLE Control 7Band2 Control 7Band6 Control 2 P Bass Setting3 3Band2 Control
2
Scaler2 Setting P V_MAX MIDDLE Frequency 7Band2 Frequency 7Band6 Frequency 2 P Treble Setting1 3Band2 Frequency
2
Main Volume Setting P V_K MIDDLE Quality factor 7Band2 Quality factor 7Band6 Quality factor 2 P Treble Setting2 3Band2 Quality factor
2
Main Balance Setting P V_OFS MIDDLE Gain 7Band2 Gain 7Band6 Gain 2 P Bass Soft_T Start 3Band2 Gain
2
PLLA Setting1 Power Stage Gain
Power Stage Test1
Power Stage Test2
Power Stage Test3
Power Stage Test4
Power Stage Test5
Sync Detect1 Power Stage Test6
Sync Detect2 Power Stage Test7
Read Base Address
PLLA Initial Setting1 C I S Format2 S-P2
2
PLLA Initial Setting2 D I S Format3 P-S1
2
PLLA Initial Setting3 E I S Format4 P-S2
2
PLLA Initial Setting4 F
B I S Format1 S-P1
I/O Setting SYSCLK SEL1 CLK Setting DSP SPDIF DSP Volume P Volume DSP TONE DSP 7Band P-EQ DSP 7Band P-EQ DSP Sound Effect DSP 3BandP-EQ
2
Main Post Scalar Setting A_RATE R_RATE TREBLE Control 7Band3 Control 7Band7 Control 2 P Treble Soft_T Start 3Band3 Control
Main Clipper ON/OFF A_TIME R_TIME TREBLE Frequency 7Band3 Frequency 7Band7 Frequency
3Band3 Frequency
Main Clipper Setting1 A_RATE_Low R_RATE_Low TREBLE Quality factor 7Band3 Quality factor 7Band7 Quality factor Sub Woofer LPF Setting 3Band3 Quality factor
Main Clipper Setting2 AR_TIME_ Low TREBLE Gain 7Band3 Gain 7Band7 Gain
Sub Volume Setting Pulse Sound Setting1 TONE Control Soft_T Start 7Band4 Control
Sub Balance Setting
Sub Post Sub Input Scalar Setting Selector
7Band4 Frequency CRAM Auto Over Write
7Band4 Quality factor CRAM Auto Setting1
7Band4 Gain CRAM Auto Setting2
3Band3 Gain
P-EQ Setting1
P-EQ Setting2
P-EQ Setting3
P-EQ Setting4
B Power Stage C2D speed C D E F TEST Mode RAM Test Setting1 Read Base Address
RAM Test Setting2
RAM Test Setting3
RAM Test Setting4
RAM Test Setting5
DSP Mute Set
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15/32
2010.05 - Rev.B
BM5446EFV
Technical Note
Format of digital audio input SYS_CLK: It is System Clock input signal. It will input LRCLK, BCLK, SDATA1 (SDATA2) that synchronizes with this clock that are 128 times of sampling frequency (128fs), 256 times of sampling frequency (256fs), or 512 times frequency (512fs) of sampling frequency (fs). LRCLK: It is L/R clock input signal. It corresponds to 32kHz/44.1kHz/48kHz with those clock (fs) that are same to the sampling frequency (fs) . The audio data of a left channel and a right channel for one sample is input to this section. BCLK: It is Bit Clock input signal. It is used for the latch of data in every one bit by sampling frequency's 48 times frequency (48fs) or 64 times sampling frequency (64fs). However if the 48fs being selected, the input will be Right-justified data format and held static. SDATA1 & SDATA2: It is Data input signal. It is amplitude data. The data length is different according to the resolution of the input digital data. It corresponds to 16/ 20/ 24 bit. The digital input has I2S, Left-justified and Right-justified formats. The figure below shows the timing chart of each transmission mode.
I2S data format
LRCLK
BCLK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
MSB SDATA S
LSB
MSB S
LSB
16bit 20bit 24bit
16bit 20bit 24bit
Left-justified data format
LRCLK
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
BCLK
MSB SDATA S 16bit 20bit 24bit
LSB
MSB S
LSB
16bit 20bit 24bit
Right-justified data format
LRCLK
BCLK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
MSB SDATA S
LSB
MSB S
LSB
16bit 20bit 24bit 24bit 20bit
16bit
Right-justified data format (48fs)
LRCLK
BCLK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
MSB SDATA S
LSB
MSB S
LSB
16bit 20bit 24bit 24bit 20bit
16bit
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16/32
2010.05 - Rev.B
BM5446EFV
Power supply start-up sequence
VCCA (27pin) VCCP1 (51, 52pin) VCCP2 (30, 31pin) REG_3 (3pin) VDD (18pin) Power up VCCA, VCCP1, VCCP2 simultaneously.
Technical Note
VCCA, VCCP1,VCCP2
REG_3, VDD
t
SYS_CLK (5pin)
Start sending SYS_CLK after REG_3 is stabilized. Send SYS_CLK before setting RESETX to High.
t
10 cycle 10 cycle or more or more BCLK LRCLK SDATA1 SDATA2 (6pin) (7pin) (8pin) (9pin) Send digital input signal before RESETX release.
t
RESETX (10pin)
Send SYS_CLK 10 cycle or more before setting RESETX to High.
t
SCL SDA
(13pin) (14pin) Release RESETX then send 10 cycle or more SYS_CLK before starting I2C BUS data communication.
t
Start data transmission
PDX (12pin)
Set PDX to High after initial setting by I2C BUS.
t
OUT_DAC1 (25pin) OUT_DAC2 (24pin) 2.5V(BIAS)
t
MUTEX (11pin)
Change MUTEX to High after FILA terminal stabilized. FILA terminal changes from 0V 2.5V by setting PDX=High.
t
Soft-start 43msec(fs=48kHz.)
Speaker output
t
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17/32
2010.05 - Rev.B
BM5446EFV
Power supply shut-down sequence
VCCA (27pin) VCCP1 (51, 52pin) VCCP2 (30, 31pin) REG_3 (3pin) VDD (18pin)
Technical Note
VCCA,VCCP1,VCCP2
Power down VCCA, VCCP1, VCCP2 simultaneously.
REG_3, VDD
t
SYS_CLK (5pin) Set RESETX to Low then input SYS_CLK for 10 cycle or more. And then stop SYS_CLK signal.
t
10 cycle or more BCLK LRCLK SDATA1 SDATA2 (6pin) (7pin) (8pin) (9pin)
Stop digital input signal.
t
RESETX (10pin) Set RESETX to Low.
t
SCL SDA
(13pin) (14pin)
t
PDX (12pin) Set PDX to Low.
t
OUT_DAC1 (25pin) OUT_DAC2 (24pin) 2.5V(BIAS)
t
MUTEX (11pin) Change MUTEX to Low.
t
Soft-mute 43msec(fs=48kHz)
Speaker output
t
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18/32
2010.05 - Rev.B
BM5446EFV
About the protection function Protection function Detecting condition Detecting condition Detecting condition Releasing condition Detecting condition Releasing condition Detecting condition Releasing condition Detecting & Releasing condition DAC Output
Technical Note
PWM Output
ERROR Output
Output short protection DC voltage protection in the speaker High temperature protection
Detecting current = 10A (TYP.) PWM output Duty=0% or 100% 43msec(fs=48kHz) above fixed Chip temperature to be above 150 (TYP.) Chip temperature to be below 120 (TYP.) Power supply voltage to be below 8V (TYP.) Power supply voltage to be above 9V (TYP.) No change to SYS_CLK more than 1usec (TYP.) Input to SYS_CLK
Normal operation HiZ_Low L (Latch) (Latch) Normal operation HiZ_Low Normal operation HiZ_Low Normal operation HiZ_Low H H H
HiZ_Low L (Latch) (Latch)
Under voltage protection
Normal operation Irregular output
Clock stop protection
Normal Normal operation operation
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19/32
2010.05 - Rev.B
BM5446EFV
Technical Note
1) Output short protection(Short to the power supply) This IC has the output short protection circuit that stops the PWM output when the PWM output is short-circuited to the power supply due to abnormality. Detecting condition - It will detect when MUTE pin is set High and the current that flows in the PWM output pin becomes 10A(TYP.) or more. The PWM output instantaneously enters the state of HiZ-Low if detected, and IC does the latch. Releasing method - After the MUTEX pin is set Low once, the MUTEX pin is set High again. Turning on the power supply again.
Short to VCC Release from short to VCC
OUT1P (48, 49pin) OUT1N (43, 44pin) OUT2P (33, 34pin) OUT2N (38, 39pin)
t
PWM outIC latches with HiZ-Low. Over current Normal operation after released from Latch state.
10A(TYP.)
t
ERROR (26pin)
t
sec(TYP.) MUTEX11pin
Latch release
t
2) Output short protection(Short to GND) BM5446EFV has the output short protection circuit that stops the PWM output when the PWM output is short-circuited to GND due to abnormality. Detecting condition - It will detect when MUTE pin is set High and the current that flows in the PWM output terminal becomes 10A(TYP.) or more. The PWM output instantaneously enters the state of HiZ-Low if detected, and IC does the latch. Releasing method - After the MUTEX pin is set Low once, the MUTEX pin is set High again. Turning on the power supply again.
Short to GND Release from short to GND
OUT1P (48, 49pin) OUT1N (43, 44pin) OUT2P (33, 34pin) OUT2N (38, 39pin)
t
PWM out IC latches with HiZ-Low state. Ovre current Normal operation after released from latch state.
10A(TYP.)
t
ERROR (26pin)
t
sec(TYP.) MUTEX(11pin)
Latch release
t
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20/32
2010.05 - Rev.B
BM5446EFV
Technical Note
3) DC voltage protection in the speaker When the DC voltage in the speaker is impressed due to abnormality, this IC has the protection circuit where the speaker is defended from destruction. Detecting condition - It will detect when MUTE pin is set High and PWM output Duty=0% or 100% , 43msec(fs=48kHz) or above. Once detected, The PWM output instantaneously enters the state of HiZ-Low, and IC does the latch. Releasing method - After the MUTEX pin is set Low once, the MUTEX pin is set High again. Turning on the power supply again
PWM out locked duty=100% abnormal state.
Abnormal state release
OUT1P (48, 49pin) OUT1N (43, 44pin) OUT2P (33, 34pin) OUT2N (38, 39pin) t PWM out IC latches with HiZ-Low state. Speaker out Latch release state.
t
Soft-start Protection start surge current into speaker output for 43 msec and over. 43msec(fs=48kHz)
ERROR (26pin)
t
MUTEX(11pin)
Latch release t
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21/32
2010.05 - Rev.B
BM5446EFV
Technical Note
4) High temperature protection BM5446EFV has the high temperature protection circuit that prevents thermal reckless driving under an abnormal state for the temperature of the chip to exceed Tjmax=150. Detecting condition - It will detect when MUTE pin is set High and the temperature of the chip becomes 150(TYP.) or more. The speaker output is muted through a soft-mute when detected. Releasing condition - It will release when MUTE pin is set High and the temperature of the chip becomes 120(TYP.) or less. The speaker output is outputted through a soft-start when released.
Temparature of IC chip junction() 150
120
t
OUT1P (48, 49pin) OUT1N (43, 44pin) OUT2P (33, 34pin) OUT2N (38, 39pin) HiZ-Low
t
Soft-mute 43msec(fs=48kHz) Speaker output Soft-start 43msec(fs=48kHz)
t
ERROR (26pin) 3.3V
t
OUT_DAC1 (25pin) OUT_DAC2 (24pin)
t
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22/32
2010.05 - Rev.B
BM5446EFV
Technical Note
5) Under voltage protection BM5446EFV has the under voltage protection circuit that make speaker output mute once detecting extreme drop of the power supply voltage. Detecting condition - It will detect when MUTE pin is set High and the power supply voltage becomes lower than 8V. The speaker output is muted through a soft-mute when detected. Releasing condition - It will release when MUTE pin is set High and the power supply voltage becomes more than 9V. The speaker output is outputted through a soft-start when released.
VCCA (27pin) VCCP1 (51, 52pin) VCCP2 (30, 31pin)
9V
8V
t
OUT1P (48, 49pin) OUT1N (43, 44pin) OUT2P (33, 34pin) OUT2N (38, 39pin) HiZ-Low
t
Soft-mute 43msec(fs=48kHz) Speaker output
Soft-start 43msec(fs=48kHz)
t
ERROR (26pin) 3.3V
t
OUT_DAC1 (25pin) OUT_DAC2 (24pin)
t
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23/32
2010.05 - Rev.B
BM5446EFV
Technical Note
6) Clock stop protection BM5446EFV has the clock stop protection circuit that make the speaker output mute when the SYS_CLK signal of the digital audio input stops. Detecting condition - It will detect when MUTE pin is set High and the SYS_CLK signal doesn't change for about 1usec or more. The speaker output is muted through a soft-mute when detected. Releasing condition - It will release when MUTE pin is set High and the SYS_CLK signal returns to the normal clock operation. The speaker output is outputted through a soft-start when released.
Clock stop Clock recover
SYS_CLK (5pin)
t
Protection start with about 1sec clock stop. BCLK (6pin)
t
OUT1P (48, 49pin) OUT1N (43, 44pin) OUT2P (33, 34pin) OUT2N (38, 39pin)
HiZ-Low State.
t
Speaker output
Soft-start (Auto recovery) 43msec(fs=48kHz)
t
ERROR (26pin)
3.3V
t
OUT_DAC1 (25pin) OUT_DAC2 (24pin)
Unstable
t
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24/32
2010.05 - Rev.B
BM5446EFV
Application Circuit Example (RL_SP=8)
Technical Note
C1 1F C2 1F C3 1F
1 2 3 4 5 6 7 8 9 10 11 12
FILP FILA REG_3 GNDA
VCCP1
REG_G1
54 NC 53
VCCP1 C54 3.3F
52 51
+
GNDA SYS_CLK BCLK Digital Audio Source LRCLK SDATA1 SDATA2 RESET MUTE -con PDX SCL SDA VSS
3.3V 10k 3.3V 10k
NC 50 49 I2S/LJ/ RJ Interface Driver 1P REG_G1 47 46 Driver 1N
GNDP1 Control Interface
C45 0.1F
220F C45D L48 22H
48
C47 1F
470pF C48B C48A 0.068F R48B 5.6 0.33F C43C R43BGNDP1 5.6 0.068F C43B C43A 470pF 22H L43 C42 1F SP 1ch (8)
45
GNDP1
44 43 REG_G1 42 NC 41 40 REG_G2 39 38 Driver 2N
GNDP2
13 14 15 16 17
I2 C Interface
DSP
PWM Modulator
C16 1F
VSS1 REG_15 TEST1 VDD PLL VSS2 REG_G2 TEST2 Driver 2P
C38 1F 22H L38 C38B 470pF GNDP2 R38B 5.6 C38A 0.068F C31C 0.33F
C18 1F C19 0.027F R19 1.5k C20 2700pF
18 19 20 21
37 36
R33B
35 34 33 NC 32
C33 1F
GNDP2 5.6 0.068F C33B C33A 470pF L33 22H
SP 2ch (8)
3.3V I2C BUS Address Select VSS OUT_SPDIF OUT_DAC2 (2ch) OUT_DAC1 (1ch) ERROR VCCA
C27D 1F C24 1F C25 3.3V
22 23 24 DAC 25 26 27 High Temperature Protection Under Voltage Protection Clock Stop Protection Output Short Protection Output DC Voltage Protection REG_G2 VCCA
VCCP2
C30 0.1F C30D 220F
+
31 30
VCCP2
100k
NC 29 28
C28 3.3F
GNDA
+
10F C27 0.1F
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25/32
2010.05 - Rev.B
BM5446EFV
BOM list(RL_SP =8)
Parts IC Parts No. U1 Value Company ROHM TOKO Inductor L33, L38, L43, L48 22H SAGAMI R33B, R38B R43B, R48B R19 C33, C38, C42, C47 C27, C30, C45 C33A, C38A C43A, C48A C31C, C43C Capacitor C28, C54 C1, C2, C3 C16, C18, C25, C24 C33B, C38B C43B, C48B C19 C20 C30D, C45D C27D 5.6 ROHM 1.5k 1F 0.1F 0.068F 0.33F 3.3F 1F 470pF 0.027F 2700pF 220F Panasonic 10F EEUFC1H100L 50V 20% MURATA MCR01MZPF1501 GRM185B31C105KE43 GRM188B31H104KA92 GRM21BB11H683KA01 GRM219B31H334KA87 GRM188B31A335KE15 GRM185B30J105KE25 GRM188B11H471KA GRM188B11C273KA01 GRM188B11E272KA01 ECA1VMH221 16V 50V 50V 50V 10V 6.3V 50V 16V 25V 35V B(10% B(10% B(10% B(10% B(10% B(10% B(10% B(10% B(10% 20% DBE7210H-220M MCR18PZHZFL5R60 1/4W (20%) F(1%) Product No. BM5446EFV 1168ER-0001 Rated Voltage Tolerance (20%)
Technical Note
Size 18.5mmx9.5mm 10.3mmx7.6mm 10.5mmx6.4mm 3.2mmx1.6mm 1.0mmx0.5mm 1.6mmx0.8mm 1.6mmx0.8mm 2.0mmx1.25mm 2.0mmx1.25mm 1.6mmx0.8mm 1.6mmx0.8mm 2.0mmx1.2mm 1.6mmx0.8mm 1.6mmx0.8mm 8mmx11.5mm 5mmx11mm
Resistor
Electrolytic Capacitor
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26/32
2010.05 - Rev.B
BM5446EFV
Application Circuit Example(RL_SP =6)
Technical Note
C1 1F C2 1F C3 1F
1 2 3 4 5 6 7 8 9 10 11 12
FILP FILA REG_3 GNDA
VCCP1
REG_G1
54 NC 53
VCCP1 C54 3.3F
52 51
+
GNDA SYS_CLK BCLK Digital Audio Source LRCLK SDATA1 SDATA2 RESET MUTE -con PDX SCL SDA VSS
C16 1F 3.3V 10k 3.3V 10k
NC 50 49 I2S/LJ/ RJ Interface Driver 1P REG_G1 47 46 Driver 1N
GNDP1 Control Interface
C45 0.1F
220F C45D L48 15H
48
C47 1F
470pF C48B C48A 0.1F 5.6 0.47F C43C GNDP1 5.6 C43B C43A 470pF 0.1F 15H L43 C42 1F SP 1ch (6)
45
GNDP1
44 43 REG_G1 42 NC 41 40 REG_G2 39 38 Driver 2N
GNDP2 C38 1F
13 14 15 16 17
I2 C Interface
DSP
PWM Modulator
VSS1 REG_15 TEST1 VDD PLL VSS2 REG_G2 TEST2 Driver 2P
15H L38 C38B 470pF C38A 0.1F GNDP2 R38B 5.6 C31C 0.47F
C18 1F C19 0.027F R19 1.5k C20 2700pF
18 19 20 21 3.3V
37 36 35 34 33 NC 32
+
C33 1F
R33BGNDP2 5.6 C33B 0.1F C33A 470pF L33 15H
SP 2ch (6)
I2C BUS Address Select VSS OUT_SPDIF OUT_DAC2 (2ch) OUT_DAC1 (1ch) ERROR VCCA
C27D 1F C24 1F C25 3.3V
22 23 24 DAC 25 26 27 High Temperature Protection Under Voltage Protection Clock Stop Protection Output Short Protection Output DC Voltage Protection REG_G2 VCCA
VCCP2
C30 0.1F C30D 220F
31 30
VCCP2
100k
NC 29 28
C28 3.3F
GNDA
+
10F C27 0.1F
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27/32
2010.05 - Rev.B
BM5446EFV
BOM list(RL_SP =6)
Parts IC Inductor Parts No. U1 L33, L38, L43, L48 R33B, R38B R43B, R48B R19 C33, C38, C42, C47 C27, C30, C45, C33A, C38A, C43A, C48A C31C, C43C C28, C54 Capacitor C1, C2, C3 C16, C18, C25, C24 C33B, C38B C43B, C48B C19 C20 C30D, C45D C27D Value 15H 5.6 ROHM 1.5k 1F 0.1F 0.47F 3.3F MURATA 1F 470pF 0.027F 2700pF 220F Panasonic 10F EEUFC1H100L 50V 20% GRM185B30J105KE25 GRM188B11H471KA GRM188B11C273KA01 GRM188B11E272KA01 ECA1VMH221 6.3V 50V 16V 25V 35V B(10% B(10% B(10% B(10% 20% MCR01MZPF1501 GRM185B31C105KE43 GRM188B31H104KA92 GRM21BB31H474KA87 GRM188B31A335KE15 16V 50V 50V 10V B(10% B(10% B(10% B(10% Company ROHM SAGAMI Product No. BM5446EFV DBE7210H-150M MCR18PZHZFL5R60 Rated Voltage 1/4W Tolerance (20%) F(1%)
Technical Note
Size 18.5mmx9.5mm 10.5mmx6.4mm 3.2mmx1.6mm 1.0mmx0.5mm 1.6mmx0.8mm 1.6mmx0.8mm 2.0mmx1.2mm 1.6mmx0.8mm 1.6mmx0.8mm 2.0mmx1.2mm 1.6mmx0.8mm 1.6mmx0.8mm 8mmx11.5mm 5mmx11mm
Resistor
Electrolytic Capacitor
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28/32
2010.05 - Rev.B
BM5446EFV
Technical Note
Output LC Filter Circuit An output filter is required to eliminate radio-frequency components exceeding the audio-frequency region supplied to a load (speaker). Because this IC uses sampling clock frequencies from 200kHz to 400kHz in the output PWM signals, the high-frequency components must be appropriately removed. This section takes an example of an LC type LPF shown in Fig.12, in which coil L and capacitor C compose a differential filter with an attenuation property of -12dB/oct. A large part of switching currents flow to capacitor C, and only a small part of the currents flow to speaker RL. This filter reduces unwanted emission this way. In addition, coil L and capacitor Cg compose a filter against in-phase components, reducing unwanted emission further. Filter constants depend on load impedances. The following are formulas to calculate values of L, C, and Cg when Q=0.707 is specified. L Cg C 45, 46 or 33, 34 L Cg Cg = Fig. 12 RL : Load impedance () fC : LPF cut off frequency (Hz) Following presents output LC filter constants with typical load impedances. fC = 30kHz C 0.68F 0.47F 0.22F fC = 40kHz L C 15H 0.47F 22H 0.33F 47H 0.15F RL L= RL 2 H
48, 49 or 38, 39
4 f C 1 2 f C RL 0 .2 C F
C=
F 2
RL 6 8 16
L 22H 33H 68H
Cg 0.15F 0.1F 0.047F
RL 6 8 16
Cg 0.1F 0.068F 0.033F
Use coils with a low direct-current resistance and with a sufficient margin of allowable currents. A high direct-current resistance causes power losses. In addition, select a closed magnetic circuit type product in normal cases to prevent unwanted emission. Use capacitors with a low equivalent series resistance, and good impedance characteristics at high frequency ranges (100kHz or higher). Also, select an item with sufficient withstand voltage because flowing massive amount of high-frequency currents is expected.
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29/32
2010.05 - Rev.B
BM5446EFV
Technical Note
Notes for use 1) Absolute maximum ratings Use of the IC in excess of absolute maximum ratings such as the applied voltage or operating temperature range may result in IC damage. Assumptions should not be made regarding the state of the IC (short mode or open mode) when such damage is suffered. A physical safety measure such as a fuse should be implemented when use of the IC in a special mode where the absolute maximum ratings may be exceeded is anticipated. 2) Power supply lines As return of current regenerated by back EMF of output coil happens, take steps such as putting capacitor between power supply and GND as a electric pathway for the regenerated current. Be sure that there is no problem with each property such as emptied capacity at lower temperature regarding electrolytic capacitor to decide capacity value. If the connected power supply does not have sufficient current absorption capacity, regenerative current will cause the voltage on the power supply line to rise, which combined with the product and its peripheral circuitry may exceed the absolute maximum ratings. It is recommended to implement a physical safety measure such as the insertion of a voltage clamp diode between the power supply and GND pins. 3) GND potential (Pin 4, 36, 37, 45, 46), VSS potential (Pin 15, 20) Any state must become the lowest voltage about GND terminal and VSS terminal. 4) Input terminal The parasitic elements are formed in the IC because of the voltage relation. The parasitic element operating causes the wrong operation and destruction. Therefore, please be careful so as not to operate the parasitic elements by impressing to input terminals lower voltage than GND and VSS. Please do not apply the voltage to the input terminal when the power-supply voltage is not impressed. 5) Setting of heat Use a thermal design that allows for a sufficient margin in light of the power dissipation (Pd) in actual operating conditions. This IC exposes its frame of the backside of package. Note that this part is assumed to use after providing heat dissipation treatment to improve heat dissipation efficiency. Try to occupy as wide as possible with heat dissipation pattern not only on the board surface but also the backside. Class D speaker amplifier is high efficiency and low heat generation by comparison with conventional Analog power amplifier. However, In case it is operated continuously by maximum output power, Power dissipation (Pdiss) may exceed package dissipation. Please consider about heat design that Power dissipation (Pdiss) does not exceed Package dissipation (Pd) in average power (Poav). (Tjmax : Maximum junction temperature=150 , Ta : Peripheral temperature[], ja : Thermal resistance of package[/W], Poav : Average power[W], : Efficiency) Package dissipation : Pd(W)=(Tjmax - Ta) / ja Power dissipation : Pdiss(W)= Poav x(1 / - 1) 6) Actions in strong magnetic field Use caution when using the IC in the presence of a strong magnetic field as doing so may cause the IC to malfunction. 7) Thermal shutdown circuit This product is provided with a built-in thermal shutdown circuit. When the thermal shutdown circuit operates, the output transistors are placed under open status. The thermal shutdown circuit is primarily intended to shut down the IC avoiding thermal runaway under abnormal conditions with a chip temperature exceeding Tjmax = 150. 8) Shorts between pins and misinstallation When mounting the IC on a board, pay adequate attention to orientation and placement discrepancies of the IC. If it is misinstalled and the power is turned on, the IC may be damaged. It also may be damaged if it is shorted by a foreign substance coming between pins of the IC or between a pin and a power supply or a pin and a GND. 9) Power supply on/off (Pin 27, 30, 31, 51, 52) In case power supply is started up, RESETX(Pin 10), MUTEX(Pin 11) and PDX (Pin 12) always should be set Low. And in case power supply is shut down, it should be set Low likewise. Then it is possible to eliminate pop noise when power supply is turned on/off. And also, all power supply terminals should start up and shut down together. 10) ERROR terminal(Pin 26) A error flag is outputted when Output short protection and DC voltage protection in the speaker are operated. These flags are the function which the condition of this product is shown in. 11) N.C. terminal (Pin 29, 32, 41, 50, 53) N.C. terminal (Non Connection Pin) does not connect to the inside circuit. Therefore, possible to use open. 12) TEST terminal (Pin 17, 21) TEST terminal connects with ground to prevent the malfunction by external noise. 13) Precautions for Spealer-setting If the impedance characteristics of the speakers at high-frequency range while increase rapidly, the IC might not have stable-operation in the resonance frequency range of the LC-filter. Therefore, consider adding damping-circuit, etc., depending on the impedance of the speaker.
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30/32
2010.05 - Rev.B
BM5446EFV
Allowable Power Dissipation
7
PCB 6.2W
Technical Note
6 5
Power Dissipation Pd W)
PCB 4.5W
4
3
PCB 2.0W
2 1
0 0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 150
Ambient Temperature:Ta( )
Measuring instrument: TH-156(Shibukawa Kuwano Electrical Instruments Co., Ltd.) Measuring conditions: Installation on ROHM's board Board size: 70mmx70mmx1.6mm(with thermal via on board) Material: FR4 The board on exposed heat sink on the back of package are connected by soldering. PCB : 1-layer board(back copper foil size: 0mmx0mm) ja=62.5/W PCB : 2-layer board(back copper foil size: 70mmx70mm)ja=27.8/W PCB : 4-layer board(back copper foil size: 70mmx70mm)ja=20.2/W
www.rohm.com (c) 2010 ROHM Co., Ltd. All rights reserved.
31/32
2010.05 - Rev.B
BM5446EFV
Ordering part number
Technical Note
B
M
5
Part No.
4
4
6
E
F
V
-
E
2
Part No.
Package EFV : HTSSOP-B54
Packaging and forming specification E2: Embossed tape and reel
HTSSOP-B54
18.50.1 (MAX 18.85 include BURR) (6.0)
54 28

Tape
+6 4 -4
Embossed carrier tape (with dry pack) 1500pcs E2
The direction is the 1pin of product is at the upper left when you hold
Quantity Direction of feed
9.50.2
7.50.1
0.50.15
1
1PIN MARK
27
0.8 S
1.0MAX
+0.05 0.17 -0.03
0.850.05
0.080.05
0.08 S 0.65 +0.05 0.22 -0.04 0.08
M
1.00.2
( reel on the left hand and you pull out the tape on the right hand
)
(5.0)
1pin
Direction of feed
(Unit : mm)
Reel
Order quantity needs to be multiple of the minimum quantity.
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32/32
2010.05 - Rev.B
Notice
Notes
No copying or reproduction of this document, in part or in whole, is permitted without the consent of ROHM Co.,Ltd. The content specified herein is subject to change for improvement without notice. The content specified herein is for the purpose of introducing ROHM's products (hereinafter "Products"). If you wish to use any such Product, please be sure to refer to the specifications, which can be obtained from ROHM upon request. Examples of application circuits, circuit constants and any other information contained herein illustrate the standard usage and operations of the Products. The peripheral conditions must be taken into account when designing circuits for mass production. Great care was taken in ensuring the accuracy of the information specified in this document. However, should you incur any damage arising from any inaccuracy or misprint of such information, ROHM shall bear no responsibility for such damage. The technical information specified herein is intended only to show the typical functions of and examples of application circuits for the Products. ROHM does not grant you, explicitly or implicitly, any license to use or exercise intellectual property or other rights held by ROHM and other parties. ROHM shall bear no responsibility whatsoever for any dispute arising from the use of such technical information. The Products specified in this document are intended to be used with general-use electronic equipment or devices (such as audio visual equipment, office-automation equipment, communication devices, electronic appliances and amusement devices). The Products specified in this document are not designed to be radiation tolerant. While ROHM always makes efforts to enhance the quality and reliability of its Products, a Product may fail or malfunction for a variety of reasons. Please be sure to implement in your equipment using the Products safety measures to guard against the possibility of physical injury, fire or any other damage caused in the event of the failure of any Product, such as derating, redundancy, fire control and fail-safe designs. ROHM shall bear no responsibility whatsoever for your use of any Product outside of the prescribed scope or not in accordance with the instruction manual. The Products are not designed or manufactured to be used with any equipment, device or system which requires an extremely high level of reliability the failure or malfunction of which may result in a direct threat to human life or create a risk of human injury (such as a medical instrument, transportation equipment, aerospace machinery, nuclear-reactor controller, fuelcontroller or other safety device). ROHM shall bear no responsibility in any way for use of any of the Products for the above special purposes. If a Product is intended to be used for any such special purpose, please contact a ROHM sales representative before purchasing. If you intend to export or ship overseas any Product or technology specified herein that may be controlled under the Foreign Exchange and the Foreign Trade Law, you will be required to obtain a license or permit under the Law.
Thank you for your accessing to ROHM product informations. More detail product informations and catalogs are available, please contact us.
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http://www.rohm.com/contact/
www.rohm.com (c) 2010 ROHM Co., Ltd. All rights reserved.
R1010A


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